1. Field of the Invention
The present invention relates generally to the packaging and mounting of semiconductor devices in electronic circuits, and in particular, to a method and apparatus for optimizing the integrity of a solder interconnection joining a substrate to an organic circuit board.
2. Description of Related Art
Modern electronic modules include microchips and other circuit components mounted on chip carrier substrates, which in turn, are mounted to printed circuit boards. In the electronics area there is a myriad of electronic components that require connection to other electronic components, or to other levels of packaging. Examples include mounting of integrated circuit chips to a metallized substrate, multilayer ceramic substrate (MLC), laminate organic substrate, glass ceramic substrate, card (direct-chip-attach), and any substrate made of composite materials meeting thermal and mechanical properties. The use of solder to join these components is well known in the art.
For example, referring to the prior art illustration of FIG. 1A, an electronic module includes a chip 10 mounted on a chip carrier substrate 30 via a solder interconnection array 20 (i.e. C4 connections) that is encased within an underfill material 25. In a second level surface mount attachment, the chip carrier 30 is connected to a card or printed wire board 80 via another solder interconnection array 40, such as a solder ball grid array (BGA) or a solder column grid array (CGA). In this second level attachment, solder balls (or columns) are first joined to the chip carrier substrate 30 assembly to form the solder interconnection grid array 40, e.g., BGA or CGA, which is then joined to the circuit board 80. In order to dissipate heat generated during normal working conditions, a heat sink 5 may then be thermally connected to the chip 10 via a thermal interface material 7.
However, in second level attachments, substantial differences in the coefficient of thermal expansion (CTE) can exist between the board 80 and the substrate 30, as is the case when the substrate is made from a ceramic material, and the board is made from an epoxy-glass composite (e.g., FR4). During thermal cycling these CTE mismatch differences can lead to fatigue damage of the solder ball interconnections. A creep load acting in concert with thermal cycling causes creep or flattening of such solder interconnections, which can result in drastic loss of Thermo-Mechanical Fatigue (TMF) reliability, causing early opens and near-opens in the interconnect structure. Whereas a full open is a fail, even a near open can have disastrous consequences on electrical performance because of a spike in circuit resistance. Thus, the accumulation of plastic strains from repeated thermal cycling undesirably deteriorates the long-term reliability of solder joint interconnections, and ultimately leads to fatigue failure of these interconnections residing between the ceramic substrate and the board.
Further adding to fatigue failure of these solder ball interconnections are the pressures applied during the process of attaching a heat sink 5 to the electronic module. For example, clamps or other pressure bearing devices are often employed in attaching the heat sink 5 to the chip 10 via a thermal interface 7. These clamps or pressure bearing devices generate compressive forces, some of which can be high, that are exerted on the topside and underside of the electronic module, as delineated by topside arrow 91 and underside arrows 92 in FIG. 1A.
As shown in FIG. 1A, the generated compressive forces 92 are applied primarily to the extremity area of the electronic circuit, i.e., that area of the electronic module surrounding the chip 10, chip carrier 30 and solder interconnection array 40 (BGA or CGA). However, the compressive forces may also be applied under the location of the interconnection array and substrate. When the compressive forces are concentrated at the peripheral area of the solder interconnection array 40, these forces are primarily applied to the board 80 and peripheral or outer solder joints 42, which in turn, causes peripheral solder joints 42 to creep or flatten. Solder joint creep flattening undesirably deteriorates the long-term reliability of the solder joints and reduces the fatigue lifetime from thermal expansion mismatch among the various components. In extreme cases, creep flattening of the outer solder interconnections can even result in shorting of adjacent interconnections in the array, which represents catastrophic failure of the electronic module itself.
As solder interconnection array sizes increase, the actual fatigue life (time until failure) of such interconnection array decreases. Further, the fatigue life of a BGA is a function of the materials that make up the substrate, board, and interconnections, the dimensions of the substrate, interconnection and board, and also the interconnection structure. Thus, present trends towards high-powered packages, coupled with higher I/O counts, and larger interconnection arrays, creates a need for interconnections with improved fatigue life, preferably fatigue lives that are significantly greater than the reasonable expected life of the electronic module itself.
There is much prior art addressed at increasing the longevity of electronic modules. For example, referring to FIG. 1B, an interposer 60 may be provided between the substrate 30 and board 80 to enhance reliability of solder interconnection array 40. In so doing, solder interconnection array 40 is now joined to the substrate 30 and the interposer 60 and is encased within an underfill material 45 for enhancing the reliability of the interconnection grid array 40 and increasing the cyclic fatigue life of the module. A second solder interconnection grid array 70 is then provided for joining the interposer 60 to the board 80, whereby this solder interconnection grid array 70 is exposed to the environment. However, this approach is not optimal in achieving a useful product life as the second solder interconnection grid array 70 is now susceptible to the deleterious effects of peripheral solder joint 72 solder creep flattening due to the pressures applied during the process of attaching the heat sink 5 to chip 10, as well from any clamping pressure maintained for the life of the assembly. Further, the addition of an interposer undesirably adds another level of hierarchy to the continually decreasing sized modern electronic component modules.
FIG. 1C illustrates another prior art method in which the underfill material only partially encases dual melt solders adjacent the substrate 30 for allowing reworkability of the electronic module. In this approach, the underfill material is dispensed and cured before the module is attached to the board. Since the underfill material only partially encapsulates the dual melt solders, the peripheral solder joints 42 of the dual melt solder interconnection grid array 41 are exposed to the environment, i.e., not underfilled, and as such, are susceptible to the deleterious effects of solder creep flattening as shown in FIG. 1C. Further in these conventional partial underfill approaches, the dual melt solder interconnection grid array 41 is first attached to the substrate 30, and then the dual melt solders are coated with the underfill material so that the underfill material only partially covers the dual melt solder. In particular, the underfill material covers the low melt solder and only a portion of the high melt solder for holding the high melt solder in place during subsequent processing and rework. Once the dual melt solders are partially coated with underfill material, the board 80 is then attached to the module, i.e. to the non-encapsulated portions of the dual melt solders. In this manner, rework of the dual melt solder interconnection is possible.
However, these conventional approaches do not account for or mitigate fatigue stresses on the dual melt solder joints as a result of reducing the effective height of the joint. These approaches are also not useful for dual melt solder interconnections due to the eutectic solder of the dual melt solder which undergoes a 3-4% volumetric expansion upon liquation during card attach, whereby the resultant hydrostatic stresses will easily rupture the cured epoxy encapsulant. Further, these conventional approaches are not useful for single melt solders because the encapsulant will have no adhesion to the single melt solder during reflow operations.
Further, while underfill processes enhance solder interconnection reliability, they are quite sensitive to the material flow properties of the liquid resin, and their success is highly dependent upon module geometry. Modules built with larger chips, e.g., greater than 20 mm on a side, and very densely populated arrays, are more difficult to underfill than those built with smaller chips. Also, this type of processing is not easily extended to large solder interconnection grid arrays, e.g., those having solder joint gap heights (i.e., the height of the gap between the substrate to the board) of about 300 microns to about 900 microns, as is the case in solder arrays residing between a substrate and a circuit board. Problems with adhesion, gap (height) filling, voiding and flow control, particularly in solder interconnection grid arrays having gap heights ranging from about 300-900 microns, are difficult to control.
Still other approaches use stiffener or backing plates pressed against the backside of the circuit board for preventing the circuit board from flexing or bending as a result of mechanically applied pressures, as well as from thermal cycling stresses. Any flexing or bending of the circuit board ultimately leads to solder creep flattening within the solder interconnection grid array joining the substrate to the board. However, the use of backing plates undesirably increases costs of the electronic module, adds additional thickness to the assembly, increases processing steps and prevents the use of capacitors or modules at the back of the board.
Thus, a need continues to exist in the art for improved methods, and the apparatus formed by such methods, for enhancing the fatigue life of solder interconnection grid arrays that have solder joint gap heights ranging from about 300-900 microns, such as those solder interconnection grid arrays that join a substrate to a circuit board. Such methods would provide solder interconnection arrays that connect a substrate to a board with significantly enhanced fatigue resistance and overall improved reliability, and as such, provide the resultant assembly with increased longevity. That is, these methods and apparatus would preferably provide mechanically strong, stable electronic modules that are able to withstand compressive forces due to externally applied pressures, and accommodate strains generated from the thermal expansion mismatch during normal working conditions.